SystemVerilog practice problems

• Basic Logic Gates (Easy)
• 2-to-1 Multiplexer (Easy)
• 3-to-8 Decoder with Enable (Easy)
• Register with Enable (Easy)
• 8-to-3 Priority Encoder (Easy)
• Rising Edge Detector (Easy)
• 4-bit Up Counter (Easy)
• 4-bit Adder with Carry (Easy)
• Odd Parity State Machine (Easy)
• Binary / Gray Code Converter (Easy)
• 8-bit Serial-In Parallel-Out Shift Register (Easy)
• Decade (Mod-10) Counter (Easy)
• Two-Flop Synchronizer (Easy)
• 8-bit ALU with Flags (Medium)
• Overlapping Sequence Detector (1011) (Medium)
• Count Leading Zeros (Medium)
• Traffic Light Controller with Pedestrian Request (Medium)
• Parameterized Barrel Rotator (Medium)
• Switch Debouncer (Medium)
• Packet Header Parser (Medium)
• Synchronous FIFO (Show-Ahead) (Medium)
• UART Transmitter (8N1) (Medium)
• Valid/Ready Pipeline Register (Medium)
• Pipelined Multiply-Add (Medium)
• Round-Robin Arbiter (Medium)
• Pulse Synchronizer (Toggle CDC) (Medium)
• Sequential Restoring Divider (Hard)
• UART Receiver (8N1) with Glitch Filter and Framing Error (Hard)
• Streaming CRC-8 (Hard)
• Skid Buffer (Fully Registered Valid/Ready) (Hard)
• Asynchronous FIFO (Gray-Code Pointers) (Hard)
• Valid/Ready Protocol Checker (Hard)