Odd Parity State Machine

Easy · Finite State Machines · SystemVerilog Constructs

Bits arrive on din, one per clock cycle. Build a Moore state machine that tells whether it has seen an odd number of 1s since the last reset.

It needs only two states:

State	Meaning	odd
EVEN	an even number of 1s so far (zero counts as even)	0
ODD	an odd number of 1s so far	1

            din = 1
      ┌─────────────────┐
      │                 ▼
   [ EVEN ]          [ ODD ]
      ▲                 │
      └─────────────────┘
            din = 1

   din = 0: stay in the same state

Ports

Port	Dir	Width	Meaning
clk	input	1	Clock. din is sampled at every rising edge.
rst	input	1	Synchronous, active-high reset (takes effect only at a rising edge).
din	input	1	The incoming bit.
odd	output	1	1 in state ODD, 0 in state EVEN.

Behavior

At every rising edge of clk:

1. If rst = 1: go to EVEN. The bit on din at that edge is not counted.
2. Else if din = 1: go to the other state (EVEN ↔ ODD).
3. Else: stay in the same state.

odd depends only on the state (that is what makes it a Moore machine): it changes only right after a rising edge, never directly when din changes. So after the edge that samples a bit, odd already includes it.

Example

edge	0 (rst)	1	2	3	4	5	6
din sampled	1	1	0	1	1	1	0
state after the edge	EVEN	ODD	ODD	EVEN	ODD	EVEN	EVEN
odd after the edge	0	1	1	0	1	0	0

Try writing the states as a typedef enum logic { EVEN, ODD } state_t;.

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