Register with Enable

Easy · Sequential Logic

Build an 8-bit register: eight D flip-flops that share a clock, a reset and a load enable. A register remembers a value between clock edges, and it is the building block of every counter, pipeline and state machine.

Ports

Port	Dir	Width	Meaning
clk	input	1	Clock. The register changes only at the rising edge of clk.
rst	input	1	Synchronous, active-high reset (it takes effect only at a rising edge).
en	input	1	Load enable.
d	input	8	Value to store.
q	output	8	The stored value (the flip-flops' outputs).

Behavior

At every rising edge of clk, in priority order:

1. If rst = 1: q <= 0. Reset wins over the enable.
2. Else if en = 1: q <= d.
3. Else: q keeps its value.

Between rising edges q never changes, whatever d, en or rst do. In particular, raising rst does not clear q until the next rising edge.

Example

edge	0	1	2	3	4	5	6
rst	1	0	0	0	0	1	0
en	0	1	0	1	1	1	0
d	8'h55	8'h3C	8'hFF	8'h81	8'h07	8'hAA	8'h11
q after the edge	8'h00	8'h3C	8'h3C	8'h81	8'h07	8'h00	8'h00

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