Easy · Combinational Logic
Build the six basic logic gates side by side. Every output is a combinational function of the two 1-bit inputs a and b: it must change as soon as the inputs change, with no clock.
| Port | Dir | Width | Meaning |
|---|---|---|---|
a | input | 1 | First input. |
b | input | 1 | Second input. |
and_out | output | 1 | a AND b: 1 only when both are 1. |
or_out | output | 1 | a OR b: 1 when at least one is 1. |
xor_out | output | 1 | a XOR b: 1 when exactly one is 1. |
nand_out | output | 1 | NOT (a AND b). |
nor_out | output | 1 | NOT (a OR b). |
not_a | output | 1 | NOT a (ignores b). |
a | b | and_out | or_out | xor_out | nand_out | nor_out | not_a |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
The SystemVerilog operators you need are & (AND), | (OR), ^ (XOR) and ~ (NOT). Watch the parentheses: ~a & b means (~a) & b, which is not NAND.
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