Easy · Arithmetic · Combinational Logic
Implement a 4-bit unsigned adder with carry-in and carry-out.
| Port | Dir | Width | Meaning |
|---|---|---|---|
a | input | 4 | Unsigned operand, 0–15. |
b | input | 4 | Unsigned operand, 0–15. |
cin | input | 1 | Carry in (adds 0 or 1). |
sum | output | 4 | Low 4 bits of a + b + cin. |
cout | output | 1 | Carry out: bit 4 of a + b + cin. |
Together, {cout, sum} is the full 5-bit result: {cout, sum} == a + b + cin, which ranges from 0 (0 + 0 + 0) to 31 (15 + 15 + 1). The circuit is purely combinational.
a | b | cin | a+b+cin | cout | sum |
|---|---|---|---|---|---|
| 3 | 4 | 0 | 7 | 0 | 7 |
| 9 | 7 | 0 | 16 | 1 | 0 |
| 15 | 0 | 1 | 16 | 1 | 0 |
| 15 | 15 | 1 | 31 | 1 | 15 |
+. The catch is expression width: in Verilog the width ofan addition is decided by its context, so a + b assigned to a 4-bit signal silently drops the carry. Concatenate the outputs on the left-hand side, {cout, sum} = ..., to give the expression a 5-bit context.
i with carryc[i] (where c[0] = cin):
sum[i] = a[i] ^ b[i] ^ c[i]c[i+1] = (a[i] & b[i]) | (c[i] & (a[i] ^ b[i]))cout = c[4].The carry "ripples" from bit 0 to bit 3, which is why this structure is slow for wide adders (and why faster carry-lookahead adders exist).
Either approach is accepted.
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