4-bit Up Counter

Easy · Counters & Timers · Sequential Logic

Build a 4-bit up counter that counts 0, 1, 2, ..., 15, 0, 1, ... while enabled, and a max flag that is high whenever the count is at its largest value.

Ports

Port	Dir	Width	Meaning
clk	input	1	Clock.
rst	input	1	Synchronous, active-high reset (takes effect only at a rising edge of clk).
en	input	1	Count enable.
count	output	4	The current count (a register).
max	output	1	Combinational: 1 exactly when count == 15, whatever en is.

Behavior

count is updated at every rising edge of clk, in priority order:

1. If rst = 1: count <= 0.
2. Else if en = 1: count <= count + 1. From 15 it wraps around to 0.
3. Else: count keeps its value.

count never changes between rising edges. max is not a register: it is computed from the current count, so it is 1 during every cycle in which count is 15, and 0 again in the cycle after the counter wraps.

Example

Counting from reset with en = 1 on every edge after reset:

edge	0 (rst)	1	2	...	15	16	17
count after the edge	0	1	2	...	15	0	1
max after the edge	0	0	0	...	1	0	0

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