Easy · Sequential Logic
Design an 8-bit serial-in, parallel-out (SIPO) shift register with a shift enable. Serial data arrives MSB first: after eight enabled shifts, the first bit received is in q[7] and the last bit received is in q[0].
| Port | Dir | Width | Meaning |
|---|---|---|---|
clk | input | 1 | Clock. All state changes happen on the rising edge. |
rst | input | 1 | Synchronous, active-high reset (takes effect only at a rising edge of clk). |
en | input | 1 | Shift enable. |
din | input | 1 | Serial data input. |
q | output | 8 | Register contents (registered output). |
At every rising edge of clk, in priority order:
rst = 1: q becomes 8'h00.en = 1: every bit moves one position toward the MSB and din enters at theLSB: q[7:1] <= q[6:0], q[0] <= din. The old q[7] is discarded.
en = 0): q keeps its value; din is ignored.q changes only on rising edges (no combinational path from din or en to q).
Receiving the byte 8'hB4 = 1011_0100, MSB first, starting from reset:
| edge | rst | en | din | q after the edge |
|---|---|---|---|---|
| 0 | 1 | x | x | 0000_0000 |
| 1 | 0 | 1 | 1 | 0000_0001 |
| 2 | 0 | 1 | 0 | 0000_0010 |
| 3 | 0 | 0 | 1 | 0000_0010 (hold: en = 0) |
| 4 | 0 | 1 | 1 | 0000_0101 |
| 5 | 0 | 1 | 1 | 0000_1011 |
| 6 | 0 | 1 | 0 | 0001_0110 |
| 7 | 0 | 1 | 1 | 0010_1101 |
| 8 | 0 | 1 | 0 | 0101_1010 |
| 9 | 0 | 1 | 0 | 1011_0100 = 8'hB4 |
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