Easy · Sequential Logic
Design a synchronous rising-edge detector. The output pulse must be high for exactly one clock cycle each time the input din changes from 0 to 1.
| Port | Dir | Width | Meaning |
|---|---|---|---|
clk | input | 1 | Clock. Everything happens on the rising edge. |
rst | input | 1 | Synchronous, active-high reset (sampled on the rising edge of clk; it takes effect only at that edge). |
din | input | 1 | Input signal, sampled on every rising edge of clk. |
pulse | output | 1 | Registered output: high for one cycle after a 0→1 transition of din. |
Call d[k] the value of din sampled at rising edge k. At every rising edge k with rst = 0, the detector updates pulse to
pulse = d[k] & ~d[k-1]so pulse changes only right after a rising edge (it is the output of a flip-flop, not a combinational function of din). If din rises before edge k, pulse is 1 during the clock cycle that follows edge k, and 0 again after edge k+1 (unless another rising edge of din was sampled at edge k+1, which is impossible for a 1-bit signal that was already 1).
din stays 1 for many cycles, there is exactly one pulse.din alternates 0,1,0,1,... every cycle, pulse is 1 every other cycle.At a rising edge where rst = 1, pulse becomes 0, and the detector forgets the input history: it behaves as if the previous sample had been 1. Consequently, the first rising edge with rst = 0 never produces a pulse, even if din = 1 there. A pulse after reset requires the detector to sample din = 0 at least once and then din = 1.
| edge k | 0 (rst=1) | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|---|
din sampled | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
pulse after the edge | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
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