Medium · Counters & Timers · Finite State Machines
Design a UART transmitter for the common 8N1 format: 8 data bits, no parity, 1 stop bit. The serial line tx idles high. A frame is:
| start bit | data bit 0 (LSB) | data bit 1 | ... | data bit 7 (MSB) | stop bit |
|---|---|---|---|---|---|
0 | data[0] | data[1] | ... | data[7] | 1 |
Every bit lasts exactly CLKS_PER_BIT clock cycles, so a frame lasts 10 * CLKS_PER_BIT cycles.
| Parameter | Default | Meaning |
|---|---|---|
CLKS_PER_BIT | 4 | Clock cycles per bit (clk frequency / baud rate), 1 <= CLKS_PER_BIT <= 65535. Your design must work for every value in this range: the hidden tests also use non-default values, including the smallest. |
| Port | Dir | Width | Meaning |
|---|---|---|---|
clk | input | 1 | Clock. |
rst | input | 1 | Synchronous, active-high reset (takes effect only at a rising edge of clk). |
start | input | 1 | Request to send data. |
data | input | 8 | Byte to send; sampled only when a request is accepted. |
tx | output | 1 | Serial output (registered, see below). |
busy | output | 1 | 1 while a frame is being sent (registered, see below). |
"Registered" means driven only by flip-flops, or by logic whose inputs are only flip-flop outputs: there is no combinational path from start, data or rst to tx or busy, so they change only right after a rising edge of clk.
rst = 1): any frame in progress is abandoned, tx = 1,busy = 0.
rst = 0, start = 1 and busy = 0(the value of busy during the cycle that ends at this edge), the transmitter captures data and starts a frame. Call this the accept edge.
tx outputs the start bit forCLKS_PER_BIT cycles, then data[0], data[1], ..., data[7], then the stop bit, each for CLKS_PER_BIT cycles. busy = 1 during exactly these 10 * CLKS_PER_BIT cycles.
data (after the accept edge) do not affect the frame being sent.start while busy = 1 is ignored (it is not queued).busy = 0 after a frame is the earliestcycle in which a new request can be accepted (at the edge that ends that cycle). So holding start = 1 continuously sends frames separated by exactly one idle (tx = 1) cycle.
busy = 0), tx = 1.CLKS_PER_BIT = 4, sending 8'hA5 = 1010_0101)Bits in transmission order: start 0, then 1,0,1,0,0,1,0,1 (LSB first), then stop 1. If the accept edge is edge 0, then tx = 0 in cycles 1–4, tx = 1 in cycles 5–8 (data[0]), tx = 0 in cycles 9–12, ..., tx = 1 in cycles 37–40 (stop bit), and busy = 1 in cycles 1–40. Cycle 41 is the first cycle with busy = 0.
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