Pipelined Multiply-Add

Implement a 3-stage pipelined multiply-add unit that computes

y = a * b + c

for a new set of operands every clock cycle. A multiplier followed by an adder is too slow to finish in one short clock period, so the work is split across pipeline registers. Each set of operands carries a valid bit through the pipeline so the consumer knows which outputs are real results.

Specification

module pipelined_mac (
    input  logic        clk,
    input  logic        rst,        // synchronous, active-high
    input  logic        in_valid,   // a, b, c hold an operation this cycle
    input  logic [7:0]  a,          // unsigned
    input  logic [7:0]  b,          // unsigned
    input  logic [15:0] c,          // unsigned
    output logic        out_valid,  // y holds a result this cycle
    output logic [16:0] y           // unsigned a*b + c
);

Arithmetic. All values are unsigned. y is the exact value of a * b + c. The

largest possible result is 255 * 255 + 65535 = 130560, which needs 17 bits, so no result ever overflows y.

Throughput. The unit accepts one operation per cycle, with no stalls: there is no

backpressure. Any cycle may or may not carry an operation (in_valid may be 0, a "bubble").

Latency: exactly 3 cycles. If in_valid = 1 during cycle k (that is, at the rising

edge that ends cycle k), then during cycle k + 3 out_valid = 1 and y is the result for those operands. out_valid must be 0 in every cycle that does not carry a result. Results come out in the same order, with the same spacing (bubbles included), as the operations went in. Outputs are registered.

Reset. rst is synchronous and active-high. A rising edge with rst = 1 clears every

valid bit in the pipeline: operations that were in flight are dropped (they never produce out_valid = 1), and an operation presented with in_valid = 1 on a reset edge is ignored. After reset, out_valid is 0 until the first operation accepted after reset comes out three cycles later. Data registers do not need to be reset.

a, b, c are ignored when in_valid = 0 (the tests drive garbage there), and y is not

checked when out_valid = 0.

How you split the work across the three stages is up to you (for example: register inputs, multiply, add).

Example

Operations in cycles 1, 2 and 4: 3*4+5 = 17, 255*255+65535 = 130560, 10*20+30 = 230. Each result appears exactly three cycles later.

cycle	in_valid	a, b, c	out_valid	y
1	1	3, 4, 5	0	–
2	1	255, 255, 65535	0	–
3	0	–	0	–
4	1	10, 20, 30	1	17
5	0	–	1	130560
6	0	–	0	–
7	0	–	1	230

Pipelined Multiply-Add

Specification

Example

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