Finite State Machines practice problems

Finite state machines are at the heart of every controller. Practice Moore and Mealy machines, sequence detectors and protocol controllers in SystemVerilog, with enums for readable state encoding.

• Odd Parity State Machine (Easy)
• Overlapping Sequence Detector (1011) (Medium)
• Traffic Light Controller with Pedestrian Request (Medium)
• UART Transmitter (8N1) (Medium)
• Round-Robin Arbiter (Medium)
• Sequential Restoring Divider (Hard)
• UART Receiver (8N1) with Glitch Filter and Framing Error (Hard)