RTL for noobies

From "what is a wire?" to your first state machine, one small page at a time.

New to digital design? This pathway teaches you to describe hardware in SystemVerilog from the very beginning. Each page explains one idea in a few minutes of reading, and along the way checkpoint problems let you prove it on the real judge before you move on.

You will build logic gates, a multiplexer, a decoder, a register, a counter, an edge detector and a state machine. Finish every checkpoint to earn a certificate on your profile.

Outline

  1. Hardware is not software
  2. Signals and wires
  3. Your first module
  4. Ports and widths
  5. Gates and operators
  6. Checkpoint: basic gates
  7. Indexes, slices and concatenation
  8. Choosing between two values
  9. Checkpoint: 2-to-1 multiplexer
  10. always_comb: logic like a recipe
  11. Checkpoint: 3-to-8 decoder
  12. The clock
  13. Flip-flops and always_ff
  14. Reset and enable
  15. Checkpoint: register with enable
  16. Counting
  17. Checkpoint: 4-bit up counter
  18. Remembering the past
  19. Checkpoint: rising edge detector
  20. State machines
  21. Writing a state machine
  22. Checkpoint: odd parity FSM
  23. How your designs are tested
  24. What's next