One bit is not much. To carry a number, you bundle several wires side by side into a vector by giving the signal a width:
logic [7:0] data; // 8 bits: data[7] ... data[0]
logic [3:0] count; // 4 bits[7:0] means "bits 7 down to 0". Bit 0 is the least significant bit, the one worth 1; bit 7 is worth 128. So an 8-bit signal holds the values 0 to 255, and a 4-bit one holds 0 to 15.
SystemVerilog numbers say how many bits they have and in which base they are written:
| Literal | Width | Base | Value |
|---|---|---|---|
4'd9 | 4 | decimal | 9 |
8'hFF | 8 | hexadecimal | 255 |
8'b0000_0101 | 8 | binary | 5 (underscores are only for reading) |
1'b1 | 1 | binary | 1 |
Ports can be vectors too:
module pass8 (
input logic [7:0] a,
output logic [7:0] y
);
assign y = a; // all 8 wires connected at once
endmodule> Keep widths matched. If you put an 8-bit value into a 4-bit signal, the top bits are > silently cut off.
RTL for noobies: step 4 of 24.