In hardware, information travels on wires. A wire carries one bit: 0 (low voltage) or 1 (high voltage). In SystemVerilog a wire, or anything else that carries a value, is called a signal.
You declare a signal with the type logic:
logic ready; // one bit
logic led_on; // another bitA signal is not a variable in the programming sense. It is a named connection in the circuit. When something drives a new value onto it, everything connected to it sees that new value.
While you simulate, a signal can also show two special values:
| Value | Meaning |
|---|---|
0 | low |
1 | high |
x | unknown: the simulator cannot tell (for example, nothing set it yet) |
z | floating: nothing drives the wire at all |
If a test says your output is x, it usually means you forgot to give it a value.
RTL for noobies: step 2 of 24.