Your first module

Your first module

Hardware is built from blocks, and in SystemVerilog a block is a module. A module has a name, a list of ports (the wires that go in and out), and a body that describes what happens inside.

module buffer (
    input  logic a,
    output logic y
);
    assign y = a;
endmodule

Read it from top to bottom:

1. module buffer ( starts a block called buffer.
2. input logic a is a 1-bit wire coming in.
3. output logic y is a 1-bit wire going out.
4. assign y = a; connects them: y always equals a.
5. endmodule closes the block.

assign is a permanent connection

assign does not run once like y = a in a program. It says "y is always driven by this expression". If a changes a million times, y follows it a million times. You can picture assign as soldering a wire.

On Gate Puzzles, every problem gives you the module header (the name and the ports) in the starter code. Your job is to fill in the body.

RTL for noobies: step 3 of 24.